gnu: Add prjtrellis.

* gnu/packages/electronics.scm (prjtrellis): New variable.

Change-Id: Iac188df00f55c06f9000fe1b688d6cded9d495fd
Signed-off-by: Maxim Cournoyer <maxim.cournoyer@gmail.com>
Modified-by: Maxim Cournoyer <maxim.cournoyer@gmail.com>
This commit is contained in:
Cayetano Santos 2025-05-02 20:47:57 +02:00 committed by Maxim Cournoyer
parent 21400ed931
commit 2ca8d38281
No known key found for this signature in database
GPG key ID: 1260E46482E63562

View file

@ -422,6 +422,65 @@ such as:
@end itemize")
(license license:expat)))
(define-public prjtrellis
(package
(name "prjtrellis")
(version "1.4")
(source
(origin
(method git-fetch)
(uri (git-reference
(url "https://github.com/YosysHQ/prjtrellis/")
(commit version)
;; Pull the bitstream database for ECP5 devices; this is useful
;; only by prjtrellis: there is no need to package it separately.
(recursive? #t)))
(file-name (git-file-name name version))
(modules '((guix build utils)))
(snippet
;; Remove bundled source code for which Guix has packages.
'(with-directory-excursion "libtrellis/3rdparty"
(for-each delete-file-recursively
'("pybind11"))))
(sha256
(base32 "0c3asdfrjmnc6q3vawn3nfghgg43iajwy2zb8kck9d3wrypbhlmc"))))
(build-system cmake-build-system)
(arguments
(list
;; The examples test directory requires nextpnr, using this package as a
;; backend, which is provided by nextpnr-ecp5: the tests are to be run
;; in this later package.
#:tests? #f
#:phases
#~(modify-phases %standard-phases
(add-after 'unpack 'chdir
(lambda _
(chdir "libtrellis")))
;; point to pybind11 include dir
(add-after 'chdir 'setenv-pybind11
(lambda* (#:key inputs #:allow-other-keys)
(setenv "PYBIND11_INCLUDE_DIR"
(string-append #$(this-package-input "pybind11")
"/include/pybind11")))))))
(native-inputs (list python))
(inputs (list openocd boost pybind11))
(synopsis "Placement and routing for ECP5 FPGAs")
(description
"Project Trellis is a Nextpnr backend compatible with ECP5 FPGAs.
The following features are currently available:
@itemize
@item logic slice functionality, including carries
@item distributed RAM inside logic slices
@item all internal interconnect
@item basic IO, including tristate
@item block RAM, using inference or manual instantiation
@item multipliers using manual instantiation
@item global networks and PLLs
@item transcievers (DCUs.)
@end itemize")
(home-page "https://github.com/YosysHQ/prjtrellis/")
(license license:expat)))
(define-public opensta
;; There are no releases, we use last commit.
(let ((commit "eb8d39a7dd81b5ca2582ad9bbce0fb6e094b3e0f")