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dac95d5cb3
* gnu/packages/patches/linux-libre-arm64-mnt-reform-revert-phy-rockchip-samsung.patch: New file. * gnu/packages/patches/linux-libre-arm64-mnt-reform-revert-rk-samsung-hdptx.patch: New file. * gnu/packages/patches/linux-libre-arm64-mnt-reform-revert-vop2-display-modes.patch: New file. * gnu/local.mk[dist_patch_DATA]: Register patches. * gnu/packages/linux.scm (%mnt-reform-revert-drm-rockchip-vop2-patch): Delete variable. (linux-libre-arm64-mnt-reform)[source]: Use new patches.
94 lines
2.8 KiB
Diff
94 lines
2.8 KiB
Diff
From 3119142ea31ec13a64fbb6246f40ca9315b49b21 Mon Sep 17 00:00:00 2001
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From: Vagrant Cascadian <vagrant@debian.org>
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Date: Sun, 15 Jun 2025 02:19:50 +0000
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Subject: [PATCH 1/3] Revert "drm/rockchip: vop2: Improve display modes
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handling on RK3588 HDMI0"
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This reverts commit d2b58a10228a906d46155eb7c15d79f39be25b37.
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---
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drivers/gpu/drm/rockchip/rockchip_drm_vop2.c | 34 --------------------
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1 file changed, 34 deletions(-)
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diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c
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index 5d7df4c3b08c..2aab2a095678 100644
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--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c
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+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c
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@@ -157,7 +157,6 @@ struct vop2_video_port {
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struct drm_crtc crtc;
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struct vop2 *vop2;
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struct clk *dclk;
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- struct clk *dclk_src;
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unsigned int id;
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const struct vop2_video_port_data *data;
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@@ -212,7 +211,6 @@ struct vop2 {
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struct clk *hclk;
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struct clk *aclk;
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struct clk *pclk;
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- struct clk *pll_hdmiphy0;
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/* optional internal rgb encoder */
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struct rockchip_rgb *rgb;
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@@ -221,8 +219,6 @@ struct vop2 {
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struct vop2_win win[];
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};
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-#define VOP2_MAX_DCLK_RATE 600000000
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-
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#define vop2_output_if_is_hdmi(x) ((x) == ROCKCHIP_VOP2_EP_HDMI0 || \
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(x) == ROCKCHIP_VOP2_EP_HDMI1)
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@@ -1055,9 +1051,6 @@ static void vop2_crtc_atomic_disable(struct drm_crtc *crtc,
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vop2_crtc_disable_irq(vp, VP_INT_DSP_HOLD_VALID);
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- if (vp->dclk_src)
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- clk_set_parent(vp->dclk, vp->dclk_src);
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-
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clk_disable_unprepare(vp->dclk);
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vop2->enable_count--;
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@@ -2078,27 +2071,6 @@ static void vop2_crtc_atomic_enable(struct drm_crtc *crtc,
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vop2_vp_write(vp, RK3568_VP_MIPI_CTRL, 0);
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- /*
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- * Switch to HDMI PHY PLL as DCLK source for display modes up
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- * to 4K@60Hz, if available, otherwise keep using the system CRU.
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- */
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- if (vop2->pll_hdmiphy0 && clock <= VOP2_MAX_DCLK_RATE) {
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- drm_for_each_encoder_mask(encoder, crtc->dev, crtc_state->encoder_mask) {
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- struct rockchip_encoder *rkencoder = to_rockchip_encoder(encoder);
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-
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- if (rkencoder->crtc_endpoint_id == ROCKCHIP_VOP2_EP_HDMI0) {
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- if (!vp->dclk_src)
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- vp->dclk_src = clk_get_parent(vp->dclk);
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-
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- ret = clk_set_parent(vp->dclk, vop2->pll_hdmiphy0);
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- if (ret < 0)
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- drm_warn(vop2->drm,
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- "Could not switch to HDMI0 PHY PLL: %d\n", ret);
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- break;
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- }
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- }
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- }
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-
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clk_set_rate(vp->dclk, clock);
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vop2_post_config(crtc);
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@@ -3270,12 +3242,6 @@ static int vop2_bind(struct device *dev, struct device *master, void *data)
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return PTR_ERR(vop2->pclk);
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}
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- vop2->pll_hdmiphy0 = devm_clk_get_optional(vop2->dev, "pll_hdmiphy0");
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- if (IS_ERR(vop2->pll_hdmiphy0)) {
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- drm_err(vop2->drm, "failed to get pll_hdmiphy0\n");
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- return PTR_ERR(vop2->pll_hdmiphy0);
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- }
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-
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vop2->irq = platform_get_irq(pdev, 0);
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if (vop2->irq < 0) {
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drm_err(vop2->drm, "cannot find irq for vop2\n");
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--
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2.50.0
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